// Copyright (C) 1953-2022 NUDT
// Verilog module name - network_outport_schedule
// Version: V4.0.20220526
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//        switch output port
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module network_outport_schedule
#(
parameter clk_period = 24'h080000//8ns
)
(
        i_clk,
        i_rst_n,
        
        iv_addr         ,   
        iv_wdata        ,
                        
        i_wr_qgc        ,
        i_rd_qgc        ,
        o_wr_qgc        ,
        ov_addr_qgc     ,
        ov_rdata_qgc    ,       
        
        i_cyclestart,
        i_qbv_or_qch,
        iv_schedule_period,  
        iv_time_slot_length,        
        
        iv_pkt_bufid ,
        iv_priority  ,
        i_desp_wr    ,
        
        ov_pkt_bufid,
        o_pkt_bufid_wr,
        i_pkt_bufid_ack, 
        
        ov_osc_state
);

// I/O
// clk & rst
input                  i_clk;
input                  i_rst_n;

input     [18:0]       iv_addr         ;   
input     [31:0]       iv_wdata        ;
input                  i_wr_qgc          ; 
input                  i_rd_qgc          ; 
output                 o_wr_qgc          ; 
output    [18:0]       ov_addr_qgc       ; 
output    [31:0]       ov_rdata_qgc      ; 

input                  i_qbv_or_qch;
input     [10:0]       iv_schedule_period;  
input     [10:0]       iv_time_slot_length; 
input                  i_cyclestart;
          
input     [8:0]        iv_pkt_bufid ;
input     [2:0]        iv_priority  ;
input                  i_desp_wr    ;

output    [8:0]        ov_pkt_bufid;
output                 o_pkt_bufid_wr;
input                  i_pkt_bufid_ack; 

output    [1:0]        ov_osc_state;     

`ifdef  COUNT_ENABLE
(*MARK_DEBUG="true"*)reg [15:0]  i_desp_count;
(*MARK_DEBUG="true"*)reg [15:0]  ov_pkt_bufid_count;
wire    o_pkt_bufid_add;
assign  o_pkt_bufid_add = o_pkt_bufid_wr&i_pkt_bufid_ack;
always @(posedge i_clk or negedge i_rst_n) 
if(~i_rst_n)    begin
   i_desp_count  <=  16'b0;
   ov_pkt_bufid_count <=  16'b0;
    end
    else    begin
       i_desp_count  <=  i_desp_count + i_desp_wr;
       ov_pkt_bufid_count <=  ov_pkt_bufid_count + o_pkt_bufid_add;
        end
`endif
             
//wire
wire       [2:0]       wv_queue_id_niq2nos; 
wire                   w_queue_id_wr_niq2nos;
wire       [7:0]       wv_queue_empty_niq2nos;  

wire       [8:0]      wv_queue_wdata_niq2nqm;
wire       [8:0]       wv_queue_waddr_niq2nqm;  
wire                   w_queue_wr_niq2nqm;       
                        
wire       [8:0]       wv_queue_raddr_nos2nqm;   
wire                   w_queue_rd_nos2nqm;

wire       [8:0]       wv_rd_queue_data_nqm2nos;
wire                   w_rd_queue_data_wr_nqm2nos;

wire       [1:0]       wv_gate_ctrl_vector_qgc2niq;
wire       [7:0]       wv_gate_ctrl_vector_qgc2nos;

wire       [2:0]       wv_schqueue_id_nos2niq;  
wire                   w_schqueue_id_wr_nos2niq;
network_input_queue network_input_queue_inst(
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                        
.iv_pkt_bufid           (iv_pkt_bufid),
.iv_ipv                 (iv_priority ),
.i_pkt_bufid_wr         (i_desp_wr   ),

.i_qbv_or_qch           (i_qbv_or_qch),

.iv_gate_ctrl_vector    (wv_gate_ctrl_vector_qgc2niq),
.iv_schdule_id          (wv_schqueue_id_nos2niq),
.i_schdule_id_wr        (w_schqueue_id_wr_nos2niq), 
                       
.ov_queue_data          (wv_queue_wdata_niq2nqm),
.ov_queue_waddr         (wv_queue_waddr_niq2nqm),
.o_queue_wr             (w_queue_wr_niq2nqm),
                 
.ov_queue_id            (wv_queue_id_niq2nos),
.o_queue_id_wr          (w_queue_id_wr_niq2nos),
.ov_queue_empty         (wv_queue_empty_niq2nos)
);

queue_gate_control 
#(
.clk_period(clk_period)
)
queue_gate_control_inst(
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),

.iv_addr                (iv_addr        ),   
.iv_wdata               (iv_wdata       ),  
                        
.i_wr                   (i_wr_qgc          ),  
.i_rd                   (i_rd_qgc          ),  
.o_wr                   (o_wr_qgc          ),  
.ov_addr                (ov_addr_qgc       ),  
.ov_rdata               (ov_rdata_qgc      ),

.i_cyclestart          (i_cyclestart       ), 
.i_qbv_or_qch           (i_qbv_or_qch        ),
.iv_schedule_period     (iv_schedule_period  ),
.iv_time_slot_length    (iv_time_slot_length ),

.ov_in_gate_ctrl_vector (wv_gate_ctrl_vector_qgc2niq),
.ov_out_gate_ctrl_vector(wv_gate_ctrl_vector_qgc2nos)
);

network_queue_manage network_queue_manage_inst(
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                        
.iv_queue_wdata         (wv_queue_wdata_niq2nqm),
.iv_queue_waddr         (wv_queue_waddr_niq2nqm),                   
.i_queue_wr             (w_queue_wr_niq2nqm),                     
                                                 
.iv_queue_raddr         (wv_queue_raddr_nos2nqm),                      
.i_queue_rd             (w_queue_rd_nos2nqm),
                        
.ov_queue_rdata         (wv_rd_queue_data_nqm2nos),
.o_queue_rdata_valid    (w_rd_queue_data_wr_nqm2nos)
);

shape_schedule shape_schedule_inst(
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                    
.iv_pkt_bufid           (wv_queue_waddr_niq2nqm),
.iv_pkt_next_bufid      (wv_queue_wdata_niq2nqm),
.iv_queue_id            (wv_queue_id_niq2nos),
.i_queue_id_wr          (w_queue_id_wr_niq2nos),
.iv_queue_empty         (wv_queue_empty_niq2nos),

.ov_schdule_id          (wv_schqueue_id_nos2niq),
.o_schdule_id_wr        (w_schqueue_id_wr_nos2niq),  
                       
.iv_gate_ctrl_vector    (wv_gate_ctrl_vector_qgc2nos),
                      
.ov_queue_raddr         (wv_queue_raddr_nos2nqm),
.o_queue_rd             (w_queue_rd_nos2nqm),
.iv_rd_queue_data       (wv_rd_queue_data_nqm2nos),
.i_rd_queue_data_wr     (w_rd_queue_data_wr_nqm2nos),
                      
.ov_pkt_bufid           (ov_pkt_bufid    ),
.o_pkt_bufid_wr         (o_pkt_bufid_wr  ),                     
.i_pkt_bufid_ack        (i_pkt_bufid_ack ),

.ov_osc_state           (ov_osc_state           )
);                              
endmodule
